For this contract position with the leading computer components manufacturer, the Pre-Si Verification Engineer will develop pre-silicon functional validation tests to verify system will meet design requirements. This candidate will create test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Additionally, s/he will analyze and use results to modify testing.

In this position, you will be a member of the team responsible for functional correctness of next generation of memory buffer/controller for high end server platforms.

Responsibilities will include but not be limited to:

• Validating designs at block or full-chip level by authoring validation plans, writing focus tests, creating templates defining coverage strategies, developing and analysing coverage monitors, creating event injectors, writing architectural and micro-architectural correctness checkers, developing BFMs (Bus Functional Model), running functional simulations, and debugging failures.
• Maintaining and enhancing the validation infrastructure by creating new tools to support validation.
• Leading a small team of engineers through any of the above.
• Working in a very team-oriented environment and interacting with engineers from other design disciplines.

Required skills:

• Bachelor`s or Master`s degree in Electrical Engineering and/or Computer Engineering and/or Computer Science
• 4+ years of experience in the area of either hardware design or verification
• 2+ years of pre-si verification work using a validation methodology such as UVM, Specman E, VMM, AVM

Preferred skills:

• Test/Check/Coverage writing experience with SystemVerilog and UVM
• Object Oriented programming
• Perl
• Experience with VCS simulator and DVE or similar GUI for waveform/RTL debug

Years of experience: 4+ required