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Job Profile
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Top Echelon Network
Memory Design Engineer
Job Location: CHANDLER, AZ
Salary: 100000 - 1
Applicant will support design and verification of internally developed memory compilers and custom memories including: SRAM, Register File, ROM, One-Time-Programmable, and CAM.
JOB REQUIREMENTS
Minimum education: BSEE
Minimum of three years experience with transistor level circuit design and layout knowledge of CMOS fabrication methods and digital circuits experience with memory design and circuit simulation experience with layout parasitic extraction and simulation tools experience with Unix shell languages knowledge of verilog modeling familiarity with layout verification tools, design rules, and rule decks.
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