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Digital IC Design Engineer
Samaritan Technical Professional
Job Location: Portland, OR

This individual will make significant contributions to all aspects of IC design for low-power implantable medical devices, including neuromodulation, pacemaker and monitoring devices. The various tasks involve concept/specification development, design partitioning and block level design, detailed design, synthesis and simulation, layout floor-planning and transistor/gate level layout, bench verification and testing, test vector development, and documentation. The individual in this position will directly interact and collaborate with system level engineers, hardware engineers, firmware engineers, and with IC design, test and layout engineers in teams located onsite as well as at remote design centers. Development tasks will involve using state-of-the-art CAD tools for the design, simulation, integration and verification of digital integrated circuits and systems.


  • Design and development of high-performance and high-reliability digital and mixed-signal integrated circuits for implantable medical products.
  • Active involvement and leadership in all aspects of IC design, including the development of functional concepts and specifications, top-level design architecture, design partitioning and block level design, detailed circuit design and simulation, layout floor-planning and transistor/gate level layout, bench verification and testing, test-vector development, and documentation.
  • Design of novel very low-power, low-voltage digital IC functional blocks (combinatorial, sequential, synchronous, asynchronous, state machines, microcontrollers, DSP, memory (RAM/ROM), etc.) using schematics as well as RTL synthesis techniques with timing and power constrained design flows. A strong grasp of sub-threshold and near-threshold digital design techniques and a good understanding of high-level tradeoffs involved in optimally implementing system functions is required.
  • Design and characterization of custom low-power, low-voltage digital library standard cells and functional blocks.


  • Advanced degrees in Electrical Engineering (MS / PhD), with relevant work in the field, is highly desirable.
  • Experience in digital IC design for very low power portable, wearable, and/or implantable applications, with a strong understanding of the high-level tradeoffs involved in using various design approaches to optimally implement system functions.
  • Experience in schematic based digital design and verification.
  • Highly skilled in Verilog, RTL synthesis and verification techniques, and in effectively applying design tools and flows for timing-constrained and power-constrained designs.
  • A strong grasp of the circuit techniques and trade-offs involved in very low-power digital design, including clock and power gating, multiple VT circuits, sub-threshold and near-threshold digital design, dynamic voltage/frequency scaling, variation-aware/variation-tolerant designs, etc.
  • Strong understanding of CMOS processes, device characteristics, and layout techniques and their effects on circuit performance.
  • Experience in generating efficient test-vectors for high-fault-coverage verification and testing (pre-silicon and post-silicon) and in post-silicon lab bench testing and verification.
  • A good understanding of digital signal-processing and basic communications theory/practice is highly desired.
  • Strong verbal communications skills and strong technical document writing skills is required.
  • Experience with the use of Cadence IC design, layout and verification tools is highly desired.
  • Experience with Unix/Linux OS, scripting languages and C/C++ is desirable.

How To Apply:
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